Exploring the impact of initial design techniques on area, timing, and power in technology mapped designs: A case study on 32-bit arithmetic logic unit

This research paper investigates the influence of different initial design techniques on area, timing, and power aspects technology-mapped designs. As a practical case study, we undertake analysis 32-bit arithmetic logic unit (ALU) utilizing two distinct adder approaches. The ALU, fundamental component all processors, comprises three major units: Adder responsible for signed unsigned number addition subtraction, Logic which handles bitwise logical operations, Shifter facilitates shift operations. designs are based ripple carry method (ALU_RCA) Sklansky (ALU_SKL), respectively. process involved established toolsets from Cadence, including NCSIM simulation verification, RTL Compiler synthesis, static timing estimation, SOC encounter tool floorplanning layout. Through this investigation, aim to shed light varying performance implications approaches in